Multilevel electronic interconnect structures for a variety of applications, particularly for forming chip carrier substrates, are well known in the art. These interconnect structures generally include several layers of conductors arranged in a predefined pattern separated by suitable insulating (dielectric) materials with vias for interconnection between layers. These structures may be used for manufacturing multi- or single chip carrier substrates and micro-electronic passive devices (inductors, capacitors or combined circuitry). Many electronic systems in fields such as the military, avionics, automotive, telecommunications, computers and portable electronics utilize components containing such structures.
A number of techniques are known for producing electronic interconnect vias in chip carrier substrates. According to one process, a dielectric material, generally ceramic or silicon coated with silicon dioxide, or a printed wiring board (PWB) is provided as a base. Conductors are formed on the base beneath the dielectric material. A hole is formed in the dielectric material, which is then sputtered, or electroless plated, and pattern plated with a metal, usually copper, to interconnect the lower level of conductors with a formed upper level. The vias formed in this manner are known as unfilled vias, since the metal does not fill the entire hole. Generally, the upper surface of the dielectric material above the unfilled vias is not planar, due to settling of the dielectric material in the vias. The non-planar surface reduces the conductors' density on the upper metal layer, and the unfilled via decreases the via capability to remove heat generated by a chip.
According to another process, a thick photoresist layer is applied on top of a patterned lower conductor level. The photoresist is patterned to define the vias, and metal, such as copper, is plated up. The photoresist is removed, and polymer dielectric material is applied to cover conductors and vias. In the next step, the polymer is polished to expose the top plated via, and upper conductor level is applied. The vias formed in this manner are known as filled vias. While filled vias provide improved overall chip carrier conductor density, and thermal and electrical properties, than unfilled vias, this process is complicated and expensive. This pattern plating process uses a thick layer of photoresist, or an expensive photosensitive dielectric, and usually results in variation in the thickness of the electroplated copper across the substrate. The variation in copper via thickness may cause problems in determining where the polishing process should stop. Stopping polishing too soon may result in vias not exposed, due to their lower thickness, while stopping polishing too late may cause a reduction of the vertical dielectric spacing below its specified limit, causing variation in the designed electrical performance of the chip carrier substrate.
Yet another process is described in U.S. Pat. No. 5,580,825 to Labunov, et al. This process utilizes aluminum for the conductors and vias, and aluminum oxide as the dielectric material. The process includes defining level conductive paths by carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide over the level conductive paths, providing an upper aluminum layer over the main aluminum layer, defining interlevel interconnections on the upper aluminum layer, and subjecting the main and upper aluminum layers to porous anodization. A barrier metal layer must be provided beneath the main aluminum layer to aid in anodization of the aluminum layers, which is then completely anodized itself.
This method suffers from a number of disadvantages. Aluminum oxide is characterized as a dielectric with a high dielectric constant and high electrical losses, so it is not suited to modern chip carrier substrates transmitting high speed signals. In addition, aluminum oxide is sensitive to cracking and has high water absorption, which can change its dielectric properties as an insulator. This process is a low yield process due to conflicting requirements of the need to completely oxidize the lower barrier layer, only after all aluminum residues are converted to aluminum oxide.
Still another process is described in Applicant's co-pending Israel Patent Application 120514. In this application, there is provided a process for manufacturing an electronic interconnect structure having aluminum conductors and filled aluminum vias, separated by a non-aluminum oxide (preferably polymeric) dielectric. The process includes the steps of depositing a first layer of aluminum over a barrier metal layer on an adhesion metal layer deposited on a base; depositing an intermediate barrier metal layer over the first layer of aluminum; patterning the intermediate barrier metal layer; depositing a second layer of aluminum over the first layer of aluminum and the remaining barrier metal; depositing an upper layer of barrier metal over the second layer of aluminum; patterning the upper layer of barrier metal; converting those portions of both layers of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; removing the exposed barrier metal and adhesion metal layers to leave exposed conductors and filled vias of aluminum; applying a non-aluminum oxide dielectric material on top of the base material and aluminum conductors and vias; and removing the dielectric material to expose a top surface of the filled aluminum vias.
Despite the fact that, in this method, the aluminum oxide is replaced by a polymeric dielectric material, and that there is no need to oxidize the lower barrier metal layer since it is removed after anodization, both of which substantially improve the processing yield relative to that of Labunov, there are still a number of disadvantages with this method. First, aluminum conductors are inferior to copper conductors because of their higher electrical resistivity. Second, aluminum conductors suffer from electro-migration, especially in high current densities, as compared to copper conductors. Third, the aluminum pad on top of the interconnect structure (chip carrier substrate) is not fully compatible with conventional chip assembly processes. Therefore, chip carrier substrates with aluminum pads or conductors require more processing steps, as compared to copper pads and conductors, which makes production more complicated and expensive.
It has now been found that low dielectric constant (k) materials provide better performance than aluminum oxide, that copper forms conductors having better performance that aluminum, and that it is possible to provide, at reasonable cost, planarized filled aluminum vias with substantially perpendicular side walls formed by an overall simple process. This provides an electronic interconnect structure which is relatively straightforward and inexpensive to manufacture, and which has high density interconnectivity and permits a stacked and landless vias configuration, with superior control and uniformity in the vertical dielectric spacing between conductors across the substrate, suitable for very high speed, high frequency chips.